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AN1568/D Interfacing Between LVDS and ECL
Prepared by: Paul Lee Logic Applications Engineer ON Semiconductor http://onsemi.com
APPLICATION NOTE
Introduction Recent growth in high-speed data transmission between high-speed ICs demand more bandwidth than ever before while still maintaining high performance, low power consumption and good noise immunity. Emitter Coupled Logic (ECL) recognized the challenge and provided high performance and good noise immune devices. ECL migrated toward low voltages to reduce the power consumption and to keep up with current technology trends by offering 3.3 V and 2.5 V Low Voltage ECL (LVECL) devices. LVDS (Low Voltage Differential Signaling) technology also addresses the needs of current high performance applications. LVDS as specified in ANSI/TIA/EIA-644 by Data Transmission Interface committee TR30.2 and IEEE 1596.3 SCI-LVDS by IEEE Scalable Coherent Interface standard (SCI) is a high speed, low power interface that is a solution in many application areas. LVDS provides an output swing of 250 mV to 400 mV with a DC offset of 1.2 V. External resistor components are required for board-to-board data transfer or clock distribution. LVECL and LVDS are both differential voltage signals, but with different output amplitude and offset. The purpose of this documentation is to show the interfacing between LVECL and LVDS. In addition, it gives interface recommendations to and from 5.0 V supplied PECL devices and negative supplied ECL or NECL
ECL levels Today's applications typically use ECL devices in the PECL mode. PECL (Positive ECL) is nothing more than supplying any ECL device with a positive power supply (VCC = +5.0 V, VEE = 0 V). In addition, ECL uses differential data transmission technology, which results in better noise immunity. Since the common mode noise is coupled onto the differential interconnect, it will be seen as a common mode modulation and will be rejected. With the trend towards low voltage systems, a new generation of ECL circuitry has been developed. The Low Voltage NECL (LVNECL) devices work using negative -3.3 V or -2.5 V power supply, or more popular positive power supplies, VCC = +3.3 V or +2.5 V and VEE = GND as LVPECL. LVECL maintains 750 mV output swing with a 0.9 V offset from VCC, which makes them ideal as peripheral components. The temperature compensated (100EL, 100LVEL, 100EP, 100LVEP) output DC levels for the different supply levels are shown in Table 1. ECL outputs are designed as an open emitter, requiring a DC path to a more negative supply than VOL. (see AND8020 for ECL Termination information). ECL standard DC input levels are also relative to VCC. Many devices are available with Voltage Input HIGH Common Mode Range (VIHCMR). These differential inputs allow processing signals with small VINPPMIN (down to 200 mV, 150 mV or even 50 mV signal levels) within an appropriate offset range. The VIHCMR ranges of ECL devices are listed in each respective data sheets.
(c) Semiconductor Components Industries, LLC, 2003
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October, 2003 - Rev. 8
Publication Order Number: AN1568/D
AN1568/D
Table 1. MC100EXXX/MC100ELXXX/LVELXXX/EPXXX/LVEPXXX (TA = 0C to +85C)
Symbol VCC VEE VOH VOH VOH VOL VOL VOL Parameter Positive Supply Voltage Negative Supply Voltage Maximum Output HIGH Level Typical Output HIGH Level Minimum Output HIGH Level Maximum Output LOW Level Typical Output LOW Level Minimum Output LOW Level 2.5 V LVPECL (Note 1) +2.5 GND 1.680 1.555 1.430 0.880 0.755 0.630 3.3 V LVPECL (Note 1) +3.3 GND 2.480 2.355 2.230 1.680 1.555 1.430 5.0 V PECL (Note 1) +5 GND 4.180 4.055 3.930 3.380 3.255 3.130 NECL GND -5.2, -4.5, -3.3 or -2.5 -0.820 -0.945 -1.070 -1.620 -1.745 -1.870 Unit V V V V V V V V
1. All levels vary 1:1 with VCC and loaded with 50 W to VCC - 2.0 V.
LVDS Levels As the name indicates, the LVDS main attribute is the low voltage amplitude levels compared to other data transmission standards, as shown in Figure 1. The LVDS specification states 250 mV to 400 mV output swing for driver/transmitter (VOUTPP). The low voltage swing levels result in low power consumption while maintaining high performance levels required by most users. In addition, LVDS uses differential data transmission technology equivalent to ECL. Furthermore, LVDS technology is not dependent on specific power supply levels like ECL technology. This signifies an easy migration path to lower supply voltages such as 3.3 V, 2.5 V, or lower voltages while still maintaining the same signaling levels and high performance. ON Semiconductor currently provides a 2.5 V 1:5 dual differential LVDS Clock Driver/Receiver (MC100EP210S).
Z = 50 W
LVDS
Z = 50 W
100 W
Figure 2. LVDS Output Definition
SIGNAL VOLTAGE
LVDS receivers require 200 mV minimum input swing within the input voltage range of 0 V to 2.4 V and can tolerate a minimum of $1.0 V ground shift between the driver's ground and the receiver's ground, since LVDS receivers have a typical driver offset voltage of 1.2 V. The common mode range of the LVDS receiver is 0.2 V to 2.2 V, and the recommended LVDS receiver input voltage range is from 0 V to 2.4 V. Common mode range of LVDS is similar to the theory of Voltage Input HIGH Common Mode Range (VIHCMR) of ECL devices. Currently more LVDS standards are being developed as LVDS technology gains in popularity.
BLVDS
PECL
3.3 V LVPECL 2.5 V LVPECL LVDS 3.3 V LVTTL/LVCMOS
Bus LVDS (BLVDS) was developed for multipoint applications. This standard is targeted at heavily loaded back planes, which reduces the impedance of the transmission line by 50% or more. By providing increased drive current, the double termination seen by the driver will be compensated.
M-LVDS
NECL/LVNECL
Figure 1. Comparison of Output Voltage Levels Standards (Figure not to Scale)
TIA TR30.2 standards group is developing another multipoint LVDS application called Multipoint LVDS (M-LVDS). The maximum data rate is 500 Mbps.
LVDS require a 100 W load resistor between the differential outputs to generate the Differential Output Voltage (VOD) with a maximum current of 2.5 mA flowing through the load resistor. This load resistor will terminate the 50 W controlled characteristic impedance line, which prevent reflections and reduces unwanted electromagnetic emission (Figure 2).
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GLVDS and SLVS
Ground referenced LVDS (GLVDS) is similar to LVDS except the driver output voltage offset is nearer to ground. The advantage of GLVDS is the use of very low power supply voltages (0.5 V). Similar standard to GLVDS is SLVS (Scalable Low-Voltage Signaling for 400 mV) by JEDEC. The interface is terminated to ground with 400mV swing and a minimum supply voltage of 0.8 V.
LVDM
LVDM is designed for double 100 W-terminated applications. The driver's output current is two times the standard LVDS, thus producing LVDS characteristic levels.
Table 2. LVDS LEVELS
LVDS Specification Symbol Transmitter VPP VOS RL IOD Receiver Input Voltage Range Differential HIGH Input Threshold Differential LOW Input Threshold -100 0 2400 +100 -100 0 2400 +100 -50 -1000 Output Differential Voltage Output Offset Voltage Load Resistor Output Differential Current 2.5 250 1125 400 1275 240 1225 27 4.5 9 500 1375 50 17 9 480 300 Parameter Min Max BLVDS Specification Min Max
Interfacing Common mode range inputs are capable of processing signals with 150 mV to 400 mV amplitude. The ECL input processes signals up to 1.0 V amplitude. The DC voltage levels should be within the voltage input HIGH common mode range (VIHCMR). To interface between these two voltage levels, capacitive coupling can be used. Only clock or coded signals should be capacitively coupled. A capacitive coupling of NRZ signals will cause problems, which can require a passive or active interfacing.
M-LVDS Specification Min Max
GLVDS Specification Min Max
LVDM Specification Min Max Unit Condition
650 2100 50 13
150 75
500 250
247 1.125 50 6
454
mV mV W mA
100
Internal To Rx Adjustable
3800 +50
-500
1000 +100
0
2400 +100
MV mV mV
Vgpd < 950 mV (Note 2) Vgpd < 950 mV (Note 2) Vgpd < 950 mV (Note 2)
-100
-100
2. Vgpd is the voltage of Ground Potential Delta across or between boards.
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Capacitive Coupling LVDS to ECL
Capacitive Coupling LVDS to ECL Using V BB
Several ECL devices provide an externally accessible VBB (VBB VCC -1.3V) reference voltage. This ECL reference voltage can be used for differential capacitive coupling. The 10 nF capacitor can be used to decouple VBB to GND. (Figure 3)
Z = 50 W 10 pF
In the layout for both interfaces, the resistors and the capacitors should be located as close as possible to the ECL input to insure reduced reflection and increased signal integrity.
Capacitive Coupling ECL to LVDS
The ECL output requires a DC current path to VEE; therefore, the pulldown termination resistors, RT, are connected to VEE. The Thevenin resistor pair represent the termination of the transmission line Z = R1 || R2 and generates an appropriate DC offset level of 1.2 V. (Figure 5)
3.3 V R1 130 W Z = 50 W 10 pF R1 130 W
LVDS
Z = 50 W
100 W
ECL VBB 1 kW
10 pF 1 kW
10 nF
ECL
Z = 50 W 10 pF R2 80 W
LVDS
Figure 3. Capacitive Coupling LVDS to ECL Using VBB
RT
RT
R2 80 W
Capacitive Coupling LVDS to ECL with External Biasing
VEE
If VBB reference voltage is not available, equivalent DC voltage can be generated using a resistor divider network. The resistor values depend on VCC and VEE voltages (Table 3). Stability is enhanced during null signal conditions if a 50 mV differential voltage is maintained between the divider networks. (Figure 4)
Table 3. Examples:
VCC = GND VCC = GND VCC = GND VEE = -5.0 V VEE = -3.3 V VEE = -2.5 V R1 = 1.2 kW R1 = 680 W R1 = 100 W VCC R1 R2 = 3.4 kW R2 = 1.0 kW R2 = 90 W
Figure 5. Capacitive Coupling ECL to LVDS
An example of capacitive coupled LVPECL (ECLinPS PlusTM Device) to LVDS is shown below. (Figure 6)
2.5 V or 3.3 V R3 3.9 kW 3.3 V R3 3.9 kW 3.3 V
R2 43 W LVPECL R2 43 W R1 237 W
10 pF
LVDS
R1 Z = 50 W 10 pF
R1 237 W ECL
10 pF R4 2 kW
R4 2 kW
LVDS
Z = 50 W
100 W
Figure 6. Capacitive Coupling LVPECL to LVDS
10 pF R2 R2
Capacitive Coupling ECL to LVDS Using VOS Reference Voltage
VEE
Figure 4. Capacitive Coupling LVDS to ECL with External Biasing
Some LVDS devices supply external offset reference voltage (VOS), which can be used for capacitive coupling. When the transmission line is very short, a parallel
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termination should be used and placed as close as possible to the coupling capacitors. (Figure 7)
3.3 V LVPECL 100 kW Z = 50 W 10 pF RT ECL Z = 50 W 10 pF 1 kW 50 W VTT VOS= 1.2 V LVDS RT ZO 100 W LVDS 2.5 V ZO VCC
50 W
1 kW
Figure 9. Interfacing 2.5 V LVPECL to LVDS with Internal 100 W Termination Resistor
1.50 V 2.5 V LVPECL Output LVDS Input
Figure 7. Capacitive Coupling ECL to LVDS Using VOS Reference Voltage
720 mV
0.78 V
Direct Interfacing
Interfacing from 2.5 V LVPECL to LVDS
Where RT = 75 W
Provided that the LVDS receiver can tolerate large input voltage peak to peak amplitude, 2.5 V LVPECL can be directly interfaced to LVDS receiver using proper ECL termination. 2.5 V LVPECL will be able to drive LVDS receiver with and without internal 100 W termination resistor. (See Figures 8, 9 and 10).
2.5 V ZO VCC
Figure 10. PSPICE Simulation Levels of 2.5V LVPECL to LVDS Interface with Example Resistor Values
Furthermore, sreies termination can be used to reduce the amplitude of the signal as described in AND8020 application note, by placing RS resistor between the driver and the transmission line. (See Figures 11, 12 and 13).
2.5 V RS ZO VCC
LVPECL ZO
100 W
LVDS
LVPECL RS ZO
100 W
LVDS
RT
RT
RT
RT
Figure 8. Interfacing 2.5 V LVPECL to LVDS with External 100 W Termination Resistor
Figure 11. Interfacing 2.5 V LVPECL to LVDS with Series RS and External 100 W Termination Resistor
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2.5 V RS ZO VCC
equations may give non-standard resistor values and when choosing resistors off the shelf, to avoid cutoff condition under worst-case scenario.
3.3 V
LVPECL RS ZO
100 W
LVDS
ZO RT RT LVPECL ZO VCC
Figure 12. Interfacing 2.5 V LVPECL to LVDS with Series RS and Internal 100 W Termination Resistor
R1 1.30 V 2.5 V LVPECL Output LVDS Input R2 R2 R1
ZO
100 W LVDS ZO
430 mV
0.87 V Where RT = 75 W RS = 43 W
Figure 14. Interfacing 3.3 V LVPECL to LVDS
3.3 V
Figure 13. PSPICE Simulation Levels of 2.5V LVPECL to LVDS Interface with Series RS Resistor
LVPECL
ZO VCC
Interfacing from 3.3 V LVPECL to LVDS
Since the output levels VOH and VOL of 3.3 V LVPECL are more positive than the input range of LVDS receiver, special interface is required. (See Figures 14 and 15). Furthermore, the open emitter design of the ECL output structure need proper termination, which can be incorporated with the resistor divider network to generate a proper LVDS DC levels (eq. 1).
R1 ) R2 + RT
(eq. 1)
ZO ZO
R1
R1 ZO
100 W
LVDS
R2
R2
The resistor divider network will divide the output common mode voltage of LVPECL (VCM(LVPECL)) to input common mode voltage of LVDS (VCM(LVDS)).
VCM(LVDS) R2 + R1 ) R2 VCM(LVPECL)
(eq. 2)
Figure 15. Interfacing LVPECL to LVDS with Internal 100 W Termination Resistor
Examples: For 50 W controlled impedance, the resistor values for 3.3V LVPECL converted to LVDS voltage levels are as follows: R1 = 55 W R2 = 95 W RT = 150 W VCM(LVPECL) = 1.9 V VCM(LVDS) = 1.2 V
Where: RT = Termination Resistor VCM(LVPECL) = Common Mode Voltage VCM(LVDS) = Common Mode Voltage 3.3 V LVPECL will be able to drive LVDS receiver with and without internal 100 W termination resistor. The above
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3.3 V LVPECL 2.37 V 850 mV VCM(LVPECL) LVDS
Interfacing from PECL to LVDS
1.52 V VCM(LVDS)
1.39 V 320 mV 1.07 V
Since the output levels VOH and VOL of 5 V PECL are more positive than the input range of LVDS receiver, special interface is required. (See Figure 18). Furthermore, the open emitter design of the ECL output structure need proper termination, which can be incorporated with the resistor divider network to generate a proper LVDS DC levels (eq. 3).
R1 ) R2 + RT
(eq. 3)
Figure 16. PSPICE Simulated Voltage Levels of 3.3 V LVPECL to LVDS Interface with Example Resistor Values
The resistor divider network will divide the output common mode voltage of PECL (VCM(PECL)) to input common mode voltage of LVDS (VCM(LVDS)).
V (LVDS) R2 + CM R1 ) R2 VCM(PECL)
(eq. 4)
Interfacing from LVDS to LVPECL
The input common mode range of the low voltage ECL line receivers are wide enough to process LVDS signals. (Figure 17)
3.3 V Z = 50 W 2.5 V or 3.3 V
Where: RT = Termination Resistor VCM(PECL) = Common Mode Voltage VCM(LVDS) = Common Mode Voltage The above equations may give non--standard resistor values and when choosing resistors off the shelf, to avoid cutoff condition under worst-case scenario.
5V
LVDS
Z = 50 W
100 W
LVPECL
ZO VCC
Figure 17. Interfacing LVDS to LVPECL
PECL ZO ZO
This direct interface is possible for all ECL devices with sufficiently low minimum differential input HIGH common mode range inputs. A differentially operated receiver's VIHCMR minimum must be 1.2 V or less (see device data sheet).
Table 4. LVDS Input Compatible Devices
EP14 EP809 LVEP11 LVEP14 LVEP16 LVEP17 LVEP34 LVEP56 LVEP91 LVEP111 LVEP210 LVEP210S LVE222 LVEL05 LVEL11 LVEL13 LVEL14 LVEL16 LVEL17 LVEL29 LVEL32 LVEL33 LVEL37 LVEL39 LVEL40 LVEL51 LVEL56 LVEL92 EL13 EL14 EL17 EL29 EL39 EL56 EL91 SG11 SG14 SG16 SG16M SG16VS SG53A SG72A SG86A SG111
R1
R1 ZO
LVDS
R2
R2
Figure 18. Interfacing 5 V PECL to LVDS
Examples: For 50 W controlled impedance, the resistor values for 5V PECL converted to LVDS voltage levels are as follows: R1 = 134 W R2 = 66 W RT = 200 W VCM(PECL) = 3.65 V VCM(LVDS) = 1.2 V
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5 V PECL 4.05 V 800 mV VCM(PECL) LVDS 3.3 V Z = 50 W 5V
LVDS 1.34 V
Z = 50 W
100 W
PECL
3.25 V VCM(LVDS)
270 mV 1.07 V
RT
RT
Figure 20. Interfacing LVDS to PECL
Figure 19. PSPICE Simulated Voltage Levels of 5 V PECL to LVDS Interface with Example Resistor Values
Interfacing Between NECL to LVDS
Interfacing from +3.3 V LVDS to +5.0 V PECL
To translate LVDS signals to PECL a differential ECL device with extended common mode range inputs (See Table 4) can be used to process and translate LVDS signals when supplied with 5.0 V $ 5% supply voltage. (See Figure 20)
GND 3.3 V
ON Semiconductor has developed level translators to interface between the different voltage levels. The MC100EP90 translates from negative supplied ECL to LVPECL. The interface from LVPECL to LVDS inputs is described above. (Figure 21)
3.3 V LVPECL
NECL
MC100EL90 or MC100EP90 LVPECL RT RT -3.3 V, -4.5 V or -5.2 V
Interface LVPECL to LVDS
LVDS
-3.3 V, -4.5 V or -5.2 V
Figure 21. Interfacing from NECL to LVDS
To interface from LVDS to negative supplied ECL the common mode range (VIHCMR) of the MC100LVEL91 for -3.3 V supply and the MC100EL91 for -4.5 V/-5.2 V supply is wide enough to process LVDS signals. (See Figure 22)
3.3 V Z = 50 W
If VCC = +5 V $ 5% supply and a VEE = -5.2 V 5% supply is available the MC10E1651 can be used.
3.3 V
GND
LVDS
Z = 50 W
100 W
LVEL91 or LVEP91
NECL
LVEL91: -3.3 V, EL91: -4.5 V, -5.2 V
RT
RT -3.3 V, -4.5 V, or -5.2 V
Figure 22. Interfacing from LVDS to NECL
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Notes
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ECLinPS Plus is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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